KVPY Sample Paper KVPY Stream-SX Model Paper-24

  • question_answer
    To get output '1' at R, for the given logic gate circuit the input values must be:

    A) X = 0, Y = 1

    B) X = 1, Y = 1

    C) X = 1, Y = 0

    D) X = 0, Y = 0

    Correct Answer: C

    Solution :

    \[R=\overline{P+Q}=\overline{(\overline{x}+y)\overline{(x\overline{y})}}\]
    \[=(\overline{\overline{x}+y}).(x\overline{y})\]
    \[=(x.\overline{y}).(x\overline{y})=x\overline{y}.\]


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